AnasSarkiz/ble-pedometer
This code defines and configures various electronic hardware components such as surface-mount resistors, crystals, diodes, transistors, connectors, and switches with their physical footprints, schematic symbols, and 3D CAD models for PCB assembly.
- Version
- 1.0.7
- License
- unset
- Stars
- 0
index.circuit.tsx
PCB
Schematic
import { A_1TS026A_1600_0553_CT } from "./imports/A_1TS026A_1600_0553_CT"
import { A_2450AT18A100E } from "./imports/A_2450AT18A100E"
import { ABM11W_48_0000MHZ_7_B1U_T3 } from "./imports/ABM11W_48_0000MHZ_7_B1U_T3"
import { AO3401A } from "./imports/AO3401A"
import { BMA400 } from "./imports/BMA400"
import { BM03B_SRSS_TB_LF__SN_ } from "./imports/BM03B_SRSS_TB_LF__SN_"
import { BM04B_SRSS_TB_LF__SN_ } from "./imports/BM04B_SRSS_TB_LF__SN_"
import { BQ25186DLHR } from "./imports/BQ25186DLHR"
import { TPS7A0233DBVR } from "./imports/TPS7A0233DBVR"
import { PowerConnections } from "./power-connections"
import { McuSignalFanout } from "./mcu-signal-fanout"
import { BQ27427YZFR } from "./imports/BQ27427YZFR"
import { CC2340R52E0RGER } from "./imports/CC2340R52E0RGER"
import { ESD5Z5_0T1G } from "./imports/ESD5Z5_0T1G"
import { SN74LVC2G66DCTR } from "./imports/SN74LVC2G66DCTR"
import { USB4105_GF_A } from "./imports/USB4105_GF_A"
import { schematicLayout } from "./schematic-layout"
import { BoardSilkscreen } from "./board-silkscreen"
import { antennaKeepoutPcbX, boardHeightMm, boardWidthMm, groundPourOutline, pcbLayout } from "./pcb-layout"
import { A_0402WGF1002TCE } from "./imports/A_0402WGF1002TCE"
import { A_0402WGF1003TCE } from "./imports/A_0402WGF1003TCE"
import { A_0402WGF4701TCE } from "./imports/A_0402WGF4701TCE"
import { A_0402WGF5101TCE } from "./imports/A_0402WGF5101TCE"
import { RCA020RLF } from "./imports/RCA020RLF"
import { CL05B104KO5NNNC } from "./imports/CL05B104KO5NNNC"
import { CL05A225MQ5NSNC } from "./imports/CL05A225MQ5NSNC"
import { CL10A106KP8NNNC } from "./imports/CL10A106KP8NNNC"
import { CL10A475KP8NNNC } from "./imports/CL10A475KP8NNNC"
import { FCC0402X105K100AT } from "./imports/FCC0402X105K100AT"
import { GJM1555C1H1R5WB01D } from "./imports/GJM1555C1H1R5WB01D"
import { LQM18DN100M70L } from "./imports/LQM18DN100M70L"
import { LQW15AN2N8G80D } from "./imports/LQW15AN2N8G80D"
export default () => (
<board
name="PedometerBoard" title="BLE Pedometer Rev A — CC2340R5 / BMA400"
width={boardWidthMm} height={boardHeightMm} layers={4} thickness="1mm" solderMaskColor="green"
minTraceWidth="0.1mm" defaultTraceWidth="0.127mm"
minViaHoleDiameter="0.3mm" minViaPadDiameter="0.45mm"
pcbStyle={{ viaHoleDiameter: "0.3mm", viaPadDiameter: "0.45mm" }}
pcbSx={{
"& chip silkscreentext": { visibility: "hidden" },
"& capacitor silkscreentext": { visibility: "hidden" },
"& resistor silkscreentext": { visibility: "hidden" },
"& inductor silkscreentext": { visibility: "hidden" },
"& pushbutton silkscreentext": { visibility: "hidden" },
"& testpoint silkscreentext": { visibility: "hidden" },
}}
allowBlindAndBuriedVias={false}
minTraceToPadEdgeClearance="0.09mm" minViaEdgeToPadEdgeClearance="0.1mm"
minPadEdgeToPadEdgeClearance="0.1mm" minBoardEdgeClearance="0.2mm"
autorouter="auto_local"
>
{/* Extra solver margin; board-level fabrication checks remain unchanged. */}
<autoroutingphase name="board_route" autorouter="auto_local"
minTraceToPadEdgeClearance="0.16mm" minViaEdgeToPadEdgeClearance="0.22mm"
minViaHoleEdgeToViaHoleEdgeClearance="0.3mm" />
<via name="V_SYS_NORTH" pcbX={pcbLayout.U1_MCU.pcbX - 0.75} pcbY={pcbLayout.U1_MCU.pcbY + 2.95}
fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.45mm"
connectsTo="net.SYS_VDD" />
{/* Enter the through via on top; expose its bottom port to the remaining net. */}
<trace name="U1_VDDS1_fanout" from=".U1_MCU > .VDDS1" to=".V_SYS_NORTH > .bottom"
width="0.2mm" pcbPath={[".V_SYS_NORTH > .bottom"]} />
<schematicsheet name="power" displayName="Power, Charging & Battery" sheetIndex={0} sheetSize="ANSI_B">
<schematicsection name="usb_input" displayName="USB-C Input & Protection" />
<schematicsection name="charger_power_path" displayName="Charger & Power Path" />
<schematicsection name="battery_gauge" displayName="Battery & Fuel Gauge" />
</schematicsheet>
<schematicsheet name="core" displayName="BLE MCU, Motion & Debug" sheetIndex={1} sheetSize="ANSI_B">
<schematicsection name="ble_mcu" displayName="BLE MCU, Clock & Rails" />
<schematicsection name="motion_sensor" displayName="Motion Sensor" />
<schematicsection name="debug_test" displayName="SWD & Test Access" />
</schematicsheet>
<schematicsheet name="interfaces" displayName="Display & RF" sheetIndex={2} sheetSize="ANSI_B">
<schematicsection name="display_interface" displayName="Power-Gated Display" />
<schematicsection name="rf_front_end" displayName="2.4 GHz RF Front End" />
</schematicsheet>
<USB4105_GF_A name="J1_USB" {...schematicLayout.J1_USB} {...pcbLayout.J1_USB} />
<BM03B_SRSS_TB_LF__SN_ name="J2_BATTERY" {...schematicLayout.J2_BATTERY} {...pcbLayout.J2_BATTERY} />
<BM04B_SRSS_TB_LF__SN_ name="J3_DISPLAY" {...schematicLayout.J3_DISPLAY} {...pcbLayout.J3_DISPLAY} />
<A_1TS026A_1600_0553_CT name="SW1_WAKE" {...schematicLayout.SW1_WAKE} {...pcbLayout.SW1_WAKE} />
<A_0402WGF5101TCE name="R1_CC1" {...schematicLayout.R1_CC1} {...pcbLayout.R1_CC1} />
<A_0402WGF5101TCE name="R2_CC2" {...schematicLayout.R2_CC2} {...pcbLayout.R2_CC2} />
<ESD5Z5_0T1G name="D1_VBUS_TVS" {...schematicLayout.D1_VBUS_TVS} {...pcbLayout.D1_VBUS_TVS} />
<CL10A475KP8NNNC name="C1_VBUS" {...schematicLayout.C1_VBUS} {...pcbLayout.C1_VBUS} />
<group name="POWER_ZONE">
<BQ25186DLHR name="U2_CHARGER" {...schematicLayout.U2_CHARGER} {...pcbLayout.U2_CHARGER} />
<BQ27427YZFR name="U3_GAUGE" {...schematicLayout.U3_GAUGE} {...pcbLayout.U3_GAUGE} />
</group>
<TPS7A0233DBVR name="U6_SYS_LDO" {...schematicLayout.U6_SYS_LDO} {...pcbLayout.U6_SYS_LDO} />
<CL10A106KP8NNNC name="C2_VSYS" {...schematicLayout.C2_VSYS} {...pcbLayout.C2_VSYS} />
<CL10A475KP8NNNC name="C3_BAT" {...schematicLayout.C3_BAT} {...pcbLayout.C3_BAT} />
<FCC0402X105K100AT name="C5_LDO_IN" {...schematicLayout.C5_LDO_IN} {...pcbLayout.C5_LDO_IN} />
<CL05A225MQ5NSNC name="C6_SYS_VDD" {...schematicLayout.C6_SYS_VDD} {...pcbLayout.C6_SYS_VDD} />
<A_0402WGF1003TCE name="R6_CE_PU" {...schematicLayout.R6_CE_PU} {...pcbLayout.R6_CE_PU} />
<A_0402WGF1002TCE name="R7_PG_PU" {...schematicLayout.R7_PG_PU} {...pcbLayout.R7_PG_PU} />
<A_0402WGF1002TCE name="R8_CHG_INT_PU" {...schematicLayout.R8_CHG_INT_PU} {...pcbLayout.R8_CHG_INT_PU} />
<FCC0402X105K100AT name="C7_GAUGE_BAT" {...schematicLayout.C7_GAUGE_BAT} {...pcbLayout.C7_GAUGE_BAT} />
<CL05A225MQ5NSNC name="C8_GAUGE_VDD" {...schematicLayout.C8_GAUGE_VDD} {...pcbLayout.C8_GAUGE_VDD} />
<A_0402WGF1002TCE name="R9_BIN_PD" {...schematicLayout.R9_BIN_PD} {...pcbLayout.R9_BIN_PD} />
<A_0402WGF1002TCE name="R10_GAUGE_INT_PU" {...schematicLayout.R10_GAUGE_INT_PU} {...pcbLayout.R10_GAUGE_INT_PU} />
<CC2340R52E0RGER name="U1_MCU" {...schematicLayout.U1_MCU} {...pcbLayout.U1_MCU} />
<LQM18DN100M70L name="L1_DCDC" {...schematicLayout.L1_DCDC} {...pcbLayout.L1_DCDC} />
<CL10A106KP8NNNC name="C9_VDDR_10U" {...schematicLayout.C9_VDDR_10U} {...pcbLayout.C9_VDDR_10U} />
<CL05B104KO5NNNC name="C10_VDDR_100N_A" {...schematicLayout.C10_VDDR_100N_A} {...pcbLayout.C10_VDDR_100N_A} />
<CL05B104KO5NNNC name="C11_VDDR_100N_B" {...schematicLayout.C11_VDDR_100N_B} {...pcbLayout.C11_VDDR_100N_B} />
<FCC0402X105K100AT name="C12_VDDD" {...schematicLayout.C12_VDDD} {...pcbLayout.C12_VDDD} />
<CL05B104KO5NNNC name="C13_VDDS1" {...schematicLayout.C13_VDDS1} {...pcbLayout.C13_VDDS1} />
<CL05B104KO5NNNC name="C14_VDDS2" {...schematicLayout.C14_VDDS2} {...pcbLayout.C14_VDDS2} />
<CL05B104KO5NNNC name="C15_VDDS3" {...schematicLayout.C15_VDDS3} {...pcbLayout.C15_VDDS3} />
<CL10A106KP8NNNC name="C16_VDDS_BULK" {...schematicLayout.C16_VDDS_BULK} {...pcbLayout.C16_VDDS_BULK} />
<ABM11W_48_0000MHZ_7_B1U_T3 name="Y1_48MHZ" {...schematicLayout.Y1_48MHZ} {...pcbLayout.Y1_48MHZ} />
<A_0402WGF1003TCE name="R11_RESET_PU" {...schematicLayout.R11_RESET_PU} {...pcbLayout.R11_RESET_PU} />
<CL05B104KO5NNNC name="C17_RESET" {...schematicLayout.C17_RESET} {...pcbLayout.C17_RESET} />
<BMA400 name="U4_ACCEL" {...schematicLayout.U4_ACCEL} {...pcbLayout.U4_ACCEL} />
<CL05B104KO5NNNC name="C18_ACCEL_VDD" {...schematicLayout.C18_ACCEL_VDD} {...pcbLayout.C18_ACCEL_VDD} />
<CL05B104KO5NNNC name="C19_ACCEL_VDDIO" {...schematicLayout.C19_ACCEL_VDDIO} {...pcbLayout.C19_ACCEL_VDDIO} />
<A_0402WGF4701TCE name="R12_I2C_SCL" {...schematicLayout.R12_I2C_SCL} {...pcbLayout.R12_I2C_SCL} />
<A_0402WGF4701TCE name="R13_I2C_SDA" {...schematicLayout.R13_I2C_SDA} {...pcbLayout.R13_I2C_SDA} />
<AO3401A name="Q1_DISPLAY_SWITCH" {...schematicLayout.Q1_DISPLAY_SWITCH} {...pcbLayout.Q1_DISPLAY_SWITCH} />
<A_0402WGF1003TCE name="R14_DISPLAY_GATE_PU" {...schematicLayout.R14_DISPLAY_GATE_PU} {...pcbLayout.R14_DISPLAY_GATE_PU} />
<SN74LVC2G66DCTR name="U5_DISPLAY_BUS_SWITCH" {...schematicLayout.U5_DISPLAY_BUS_SWITCH} {...pcbLayout.U5_DISPLAY_BUS_SWITCH} />
<A_0402WGF1003TCE name="R15_DISPLAY_BUS_EN_PD" {...schematicLayout.R15_DISPLAY_BUS_EN_PD} {...pcbLayout.R15_DISPLAY_BUS_EN_PD} />
<CL10A475KP8NNNC name="C20_DISPLAY_BULK" {...schematicLayout.C20_DISPLAY_BULK} {...pcbLayout.C20_DISPLAY_BULK} />
<GJM1555C1H1R5WB01D name="C21_RF_FILTER_IN" {...schematicLayout.C21_RF_FILTER_IN} {...pcbLayout.C21_RF_FILTER_IN} />
<LQW15AN2N8G80D name="L2_RF_FILTER" {...schematicLayout.L2_RF_FILTER} {...pcbLayout.L2_RF_FILTER} />
<GJM1555C1H1R5WB01D name="C22_RF_FILTER_OUT" {...schematicLayout.C22_RF_FILTER_OUT} {...pcbLayout.C22_RF_FILTER_OUT} />
<capacitor name="C23_RF_TUNE_IN" {...schematicLayout.C23_RF_TUNE_IN} capacitance="1pF" footprint="0402" doNotPlace {...pcbLayout.C23_RF_TUNE_IN} />
<RCA020RLF name="R16_RF_TUNE_SERIES" {...schematicLayout.R16_RF_TUNE_SERIES} {...pcbLayout.R16_RF_TUNE_SERIES} />
<capacitor name="C24_RF_TUNE_OUT" {...schematicLayout.C24_RF_TUNE_OUT} capacitance="1pF" footprint="0402" doNotPlace {...pcbLayout.C24_RF_TUNE_OUT} />
<A_2450AT18A100E name="ANT1" {...schematicLayout.ANT1} {...pcbLayout.ANT1} />
<keepout shape="rect" width="5.4mm" height="7mm" pcbX={antennaKeepoutPcbX} pcbY={4.2} layers={["inner1", "inner2", "bottom"]} excludeRefs={[".ANT1"]} />
<keepout shape="rect" width="5.4mm" height="2.8mm" pcbX={antennaKeepoutPcbX} pcbY={1.3} layers={["top"]} excludeRefs={[".ANT1"]} />
<keepout shape="rect" width="5.4mm" height="2.8mm" pcbX={antennaKeepoutPcbX} pcbY={7.1} layers={["top"]} excludeRefs={[".ANT1"]} />
<testpoint name="TP1_SWDIO" {...schematicLayout.TP1_SWDIO} footprintVariant="pad" padDiameter="1.2mm" {...pcbLayout.TP1_SWDIO} connections={{ pin1: "net.SWDIO" }} />
<testpoint name="TP2_SWDCK" {...schematicLayout.TP2_SWDCK} footprintVariant="pad" padDiameter="1.2mm" {...pcbLayout.TP2_SWDCK} connections={{ pin1: "net.SWDCK" }} />
<testpoint name="TP3_RESET" {...schematicLayout.TP3_RESET} footprintVariant="pad" padDiameter="1.2mm" {...pcbLayout.TP3_RESET} connections={{ pin1: "net.RESET_N" }} />
<testpoint name="TP4_GND" {...schematicLayout.TP4_GND} footprintVariant="pad" padDiameter="1.2mm" {...pcbLayout.TP4_GND} connections={{ pin1: "net.GND" }} />
<testpoint name="TP5_SYS_VDD" {...schematicLayout.TP5_SYS_VDD} footprintVariant="pad" padDiameter="1.2mm" {...pcbLayout.TP5_SYS_VDD} connections={{ pin1: "net.SYS_VDD" }} />
<testpoint name="TP6_CHG_PG" {...schematicLayout.TP6_CHG_PG} footprintVariant="pad" padDiameter="1.0mm" {...pcbLayout.TP6_CHG_PG} connections={{ pin1: "net.CHG_PG_N" }} />
{/* USB-C sink and protected 5 V input. Data contacts are intentionally NC. */}
<trace name="J1_USB_VBUS1_to_net_VBUS" from=".J1_USB > .VBUS1" to="net.VBUS" width="0.4mm" /><trace name="J1_USB_VBUS2_to_net_VBUS" from=".J1_USB > .VBUS2" to="net.VBUS" width="0.4mm" />
<trace name="J1_USB_VBUS3_to_net_VBUS" from=".J1_USB > .VBUS3" to="net.VBUS" width="0.4mm" /><trace name="J1_USB_VBUS4_to_net_VBUS" from=".J1_USB > .VBUS4" to="net.VBUS" width="0.4mm" />
<trace name="J1_USB_GND1_to_net_GND" from=".J1_USB > .GND1" to="net.GND" width="0.4mm" /><trace name="J1_USB_GND2_to_net_GND" from=".J1_USB > .GND2" to="net.GND" width="0.4mm" />
<trace name="J1_USB_GND3_to_net_GND" from=".J1_USB > .GND3" to="net.GND" width="0.4mm" /><trace name="J1_USB_GND4_to_net_GND" from=".J1_USB > .GND4" to="net.GND" width="0.4mm" />
<trace name="J1_USB_pin1_to_net_GND" from=".J1_USB > .pin1" to="net.GND" width="0.4mm" /><trace name="J1_USB_pin2_to_net_GND" from=".J1_USB > .pin2" to="net.GND" width="0.4mm" />
<trace name="J1_USB_pin3_to_net_GND" from=".J1_USB > .pin3" to="net.GND" width="0.4mm" /><trace name="J1_USB_pin4_to_net_GND" from=".J1_USB > .pin4" to="net.GND" width="0.4mm" />
<trace name="J1_USB_CC1_to_R1_CC1_pin1" from=".J1_USB > .CC1" to=".R1_CC1 > .pin1" /><trace name="R1_CC1_pin2_to_net_GND" from=".R1_CC1 > .pin2" to="net.GND" />
<trace name="J1_USB_CC2_to_R2_CC2_pin1" from=".J1_USB > .CC2" to=".R2_CC2 > .pin1" /><trace name="R2_CC2_pin2_to_net_GND" from=".R2_CC2 > .pin2" to="net.GND" />
<trace name="D1_VBUS_TVS_C_to_net_VBUS" from=".D1_VBUS_TVS > .C" to="net.VBUS" /><trace name="D1_VBUS_TVS_A_to_net_GND" from=".D1_VBUS_TVS > .A" to="net.GND" />
<trace name="C1_VBUS_pin1_to_net_VBUS" from=".C1_VBUS > .pin1" to="net.VBUS" /><trace name="C1_VBUS_pin2_to_net_GND" from=".C1_VBUS > .pin2" to="net.GND" />
<PowerConnections />
{/* Battery connector and gauge use the BQ27427's integrated 7 mΩ sense path. */}
<trace name="J2_BATTERY_BATTERY_POS_to_net_BAT_CELL" from=".J2_BATTERY > .BATTERY_POS" to="net.BAT_CELL" width="0.4mm" /><trace name="J2_BATTERY_NTC_to_net_BATT_NTC" from=".J2_BATTERY > .NTC" to="net.BATT_NTC" />
<trace name="J2_BATTERY_GND_to_net_GND" from=".J2_BATTERY > .GND" to="net.GND" width="0.4mm" /><trace name="J2_BATTERY_MOUNT1_to_net_GND" from=".J2_BATTERY > .MOUNT1" to="net.GND" /><trace name="J2_BATTERY_MOUNT2_to_net_GND" from=".J2_BATTERY > .MOUNT2" to="net.GND" />
<trace name="U3_GAUGE_BAT_to_net_BAT_CELL" from=".U3_GAUGE > .BAT" to="net.BAT_CELL" width="0.12mm" /><trace name="U3_GAUGE_SRX_to_net_BAT_SENSED" from=".U3_GAUGE > .SRX" to="net.BAT_SENSED" width="0.12mm" />
<trace name="U3_GAUGE_VSS1_to_net_GND" from=".U3_GAUGE > .VSS1" to="net.GND" width="0.1mm" />
<trace name="U3_GAUGE_VSS2_to_net_GND" from=".U3_GAUGE > .VSS2" to="net.GND" width="0.1mm" />
<trace name="U3_GAUGE_BIN_to_R9_BIN_PD_pin1" from=".U3_GAUGE > .BIN" to=".R9_BIN_PD > .pin1" width="0.1mm" /><trace name="R9_BIN_PD_pin2_to_net_GND" from=".R9_BIN_PD > .pin2" to="net.GND" />
<trace name="C7_GAUGE_BAT_pin1_to_net_BAT_CELL" from=".C7_GAUGE_BAT > .pin1" to="net.BAT_CELL" /><trace name="C7_GAUGE_BAT_pin2_to_net_GND" from=".C7_GAUGE_BAT > .pin2" to="net.GND" />
<trace name="U3_GAUGE_VDD_to_C8_GAUGE_VDD_pin1" from=".U3_GAUGE > .VDD" to=".C8_GAUGE_VDD > .pin1" maxLength="20mm" /><trace name="C8_GAUGE_VDD_pin2_to_net_GND" from=".C8_GAUGE_VDD > .pin2" to="net.GND" maxLength="20mm" />
<trace name="U3_GAUGE_SCL_to_net_I2C_SCL" from=".U3_GAUGE > .SCL" to="net.I2C_SCL" width="0.1mm" /><trace name="U3_GAUGE_SDA_to_net_I2C_SDA" from=".U3_GAUGE > .SDA" to="net.I2C_SDA" width="0.1mm" />
<trace name="U3_GAUGE_GPOUT_to_net_GAUGE_INT_N" from=".U3_GAUGE > .GPOUT" to="net.GAUGE_INT_N" width="0.1mm" /><trace name="R10_GAUGE_INT_PU_pin1_to_net_GAUGE_INT_N" from=".R10_GAUGE_INT_PU > .pin1" to="net.GAUGE_INT_N" /><trace name="R10_GAUGE_INT_PU_pin2_to_net_SYS_VDD" from=".R10_GAUGE_INT_PU > .pin2" to="net.SYS_VDD" />
{/* MCU supplies, clock, SWD and GPIO map. */}
<trace name="U1_MCU_VDDS1_to_net_SYS_VDD" from=".U1_MCU > .VDDS1" to="net.SYS_VDD" width="0.3mm" /><trace name="U1_MCU_VDDS2_to_net_SYS_VDD" from=".U1_MCU > .VDDS2" to="net.SYS_VDD" width="0.3mm" /><trace name="U1_MCU_VDDS3_to_net_SYS_VDD" from=".U1_MCU > .VDDS3" to="net.SYS_VDD" width="0.3mm" />
<trace name="U1_GND_to_EP" from=".U1_MCU > .GND" to=".U1_MCU > .EP"
width="0.1mm" pcbPath={[".U1_MCU > .EP"]} />
{/* Local coordinates rotate with U1; escape between the two corner pins.
C13 ground remains on GND. This is authored copper, not a routing hint. */}
<trace name="U1_EP_to_C13_GND" from=".U1_MCU > .EP" to=".C13_VDDS1 > .pin2"
width="0.1mm" pcbPathRelativeTo=".U1_MCU > .EP"
pcbPath={[{ x: -1.5, y: -1.5 }, { x: -2.5, y: -2.5 }]} />
<trace name="U1_MCU_VDDR1_to_net_VDDR" from=".U1_MCU > .VDDR1" to="net.VDDR" width="0.3mm" />
<via name="V_VDDR_SOUTH" pcbX={pcbLayout.U1_MCU.pcbX - 0.65} pcbY={pcbLayout.U1_MCU.pcbY - 2.7}
fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.45mm" connectsTo="net.VDDR" />
<via name="V_VDDR_EAST" pcbX={pcbLayout.U1_MCU.pcbX + 2.6} pcbY={pcbLayout.U1_MCU.pcbY - 1}
fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.45mm" connectsTo="net.VDDR" />
<trace name="U1_VDDR2_escape" from=".U1_MCU > .VDDR2" to=".V_VDDR_SOUTH > .bottom"
width="0.2mm" pcbPath={[".V_VDDR_SOUTH > .bottom"]} />
<trace name="U1_VDDR1_escape" from=".U1_MCU > .VDDR1" to=".V_VDDR_EAST > .bottom"
width="0.2mm" pcbPath={[".V_VDDR_EAST > .bottom"]} />
<trace name="VDDR_bottom_bridge" from=".V_VDDR_SOUTH > .bottom" to=".V_VDDR_EAST > .bottom"
width="0.2mm" pcbPath={[".V_VDDR_EAST > .bottom"]} />
<trace name="U1_MCU_DCDC_to_L1_DCDC_pin1" from=".U1_MCU > .DCDC" to=".L1_DCDC > .pin1" width="0.3mm" /><trace name="L1_DCDC_pin2_to_net_VDDR" from=".L1_DCDC > .pin2" to="net.VDDR" width="0.3mm" />
<trace name="C9_VDDR_10U_pin1_to_net_VDDR" from=".C9_VDDR_10U > .pin1" to="net.VDDR" /><trace name="C9_VDDR_10U_pin2_to_net_GND" from=".C9_VDDR_10U > .pin2" to="net.GND" />
<trace name="C10_VDDR_100N_A_pin1_to_net_VDDR" from=".C10_VDDR_100N_A > .pin1" to="net.VDDR" /><trace name="C10_VDDR_100N_A_pin2_to_net_GND" from=".C10_VDDR_100N_A > .pin2" to="net.GND" />
<trace name="C11_VDDR_100N_B_pin1_to_net_VDDR" from=".C11_VDDR_100N_B > .pin1" to="net.VDDR" /><trace name="C11_VDDR_100N_B_pin2_to_net_GND" from=".C11_VDDR_100N_B > .pin2" to="net.GND" />
<trace name="U1_MCU_VDDD_to_C12_VDDD_pin1" from=".U1_MCU > .VDDD" to=".C12_VDDD > .pin1" maxLength="10mm"
pcbPathRelativeTo=".U1_MCU > .VDDD" pcbPath={[{ x: 3.7, y: 0.65 }]} />
<trace name="C12_VDDD_pin2_to_net_GND" from=".C12_VDDD > .pin2" to="net.GND" maxLength="10mm" />
<trace name="C13_VDDS1_pin1_to_net_SYS_VDD" from=".C13_VDDS1 > .pin1" to="net.SYS_VDD" /><trace name="C13_VDDS1_pin2_to_net_GND" from=".C13_VDDS1 > .pin2" to="net.GND" />
<trace name="C14_VDDS2_pin1_to_net_SYS_VDD" from=".C14_VDDS2 > .pin1" to="net.SYS_VDD" /><trace name="C14_VDDS2_pin2_to_net_GND" from=".C14_VDDS2 > .pin2" to="net.GND" />
<trace name="C15_VDDS3_pin1_to_net_SYS_VDD" from=".C15_VDDS3 > .pin1" to="net.SYS_VDD" /><trace name="C15_VDDS3_pin2_to_net_GND" from=".C15_VDDS3 > .pin2" to="net.GND" />
<trace name="C16_VDDS_BULK_pin1_to_net_SYS_VDD" from=".C16_VDDS_BULK > .pin1" to="net.SYS_VDD" /><trace name="C16_VDDS_BULK_pin2_to_net_GND" from=".C16_VDDS_BULK > .pin2" to="net.GND" />
<trace name="U1_MCU_X48P_to_Y1_48MHZ_pin1" from=".U1_MCU > .X48P" to=".Y1_48MHZ > .pin1"
pcbPathRelativeTo=".U1_MCU > .X48P" pcbPath={[{ x: 0.25, y: 3.15 }]} />
<trace name="U1_MCU_X48N_to_Y1_48MHZ_pin3" from=".U1_MCU > .X48N" to=".Y1_48MHZ > .pin3"
pcbPathRelativeTo=".U1_MCU > .X48N"
pcbPath={[{ x: -0.25, y: 2.6 }, { x: -1.2, y: 2.6 }, { x: -1.2, y: 5.2 }]} />
<trace name="Y1_48MHZ_GND1_to_net_GND" from=".Y1_48MHZ > .GND1" to="net.GND" /><trace name="Y1_48MHZ_GND2_to_net_GND" from=".Y1_48MHZ > .GND2" to="net.GND" />
<trace name="U1_MCU_RSTN_to_R11_RESET_PU_pin1" from=".U1_MCU > .RSTN" to=".R11_RESET_PU > .pin1" maxLength="15mm" /><trace name="R11_RESET_PU_pin1_to_C17_RESET_pin1" from=".R11_RESET_PU > .pin1" to=".C17_RESET > .pin1" maxLength="15mm" /><trace name="R11_RESET_PU_pin2_to_net_SYS_VDD" from=".R11_RESET_PU > .pin2" to="net.SYS_VDD" />
<trace name="C17_RESET_pin1_to_net_RESET_N" from=".C17_RESET > .pin1" to="net.RESET_N" /><trace name="C17_RESET_pin2_to_net_GND" from=".C17_RESET > .pin2" to="net.GND" />
<trace name="U1_SWDIO_to_TP1" from=".U1_MCU > .DIO16_SWDIO" to=".TP1_SWDIO > .pin1"
pcbPathRelativeTo=".U1_MCU > .DIO16_SWDIO"
pcbPath={[
{ x: -1.25, y: -2.75 },
{ x: -1.25, y: -2.75, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: -1.25, y: -2.75 },
{ x: -2.1, y: -4.2 },
{ x: 3.6, y: -9.2 },
{ x: 3.6, y: -9.2, via: true, fromLayer: "bottom", toLayer: "top" },
{ x: 3.6, y: -9.2 },
]} />
<trace name="U1_SWDCK_to_TP2" from=".U1_MCU > .DIO17_SWDCK" to=".TP2_SWDCK > .pin1"
pcbPathRelativeTo=".U1_MCU > .DIO17_SWDCK"
pcbPath={[
{ x: -0.75, y: -3.2 }, { x: -0.35, y: -3.55 },
{ x: -0.35, y: -3.55, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: -0.35, y: -3.55 },
{ x: 4.5, y: -8.6 }, { x: 4.5, y: -9.9 }, { x: 2.5, y: -9.9 },
{ x: 1.4, y: -9.2 },
{ x: 1.4, y: -9.2, via: true, fromLayer: "bottom", toLayer: "top" },
{ x: 1.4, y: -9.2 },
]} />
<trace name="U1_MCU_DIO12_to_net_I2C_SDA" from=".U1_MCU > .DIO12" to="net.I2C_SDA" width="0.1mm" /><trace name="U1_MCU_DIO24_A7_to_net_I2C_SCL" from=".U1_MCU > .DIO24_A7" to="net.I2C_SCL" width="0.1mm" />
<trace name="U1_MCU_DIO8_to_net_ACCEL_INT1" from=".U1_MCU > .DIO8" to="net.ACCEL_INT1" />
{/* Escape INT2 straight out of the pin row before changing layers. */}
<trace name="U1_DIO11_to_U4_INT2" from=".U1_MCU > .DIO11" to=".U4_ACCEL > .INT2"
pcbPathRelativeTo=".U1_MCU > .DIO11"
pcbPath={[
{ x: -2.8, y: -0.25 },
{ x: -2.8, y: -0.25, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: -2.8, y: -0.25 },
{ x: -6, y: 10.5 },
{ x: -6, y: 10.5, via: true, fromLayer: "bottom", toLayer: "top" },
{ x: -6, y: 10.5 },
]} />
<trace name="U1_MCU_DIO13_to_net_DISP_PWR_N" from=".U1_MCU > .DIO13" to="net.DISP_PWR_N" /><trace name="U1_MCU_DIO4_X32N_to_net_DISP_BUS_EN" from=".U1_MCU > .DIO4_X32N" to="net.DISP_BUS_EN" />
<trace name="U1_MCU_DIO20_A11_to_net_GAUGE_INT_N" from=".U1_MCU > .DIO20_A11" to="net.GAUGE_INT_N" /><trace name="U1_MCU_DIO21_A10_to_net_CHG_INT_N" from=".U1_MCU > .DIO21_A10" to="net.CHG_INT_N" width="0.1mm" />
<trace name="U1_CE_to_R6" from=".U1_MCU > .DIO3_X32P" to=".R6_CE_PU > .pin1"
pcbPathRelativeTo=".U1_MCU > .DIO3_X32P"
pcbPath={[
{ x: 3.1, y: -0.4 },
{ x: 3.1, y: -0.4, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: 3.1, y: -0.4 }, { x: 29.932816, y: 11.6 },
{ x: 29.932816, y: 11.6, via: true, fromLayer: "bottom", toLayer: "top" },
{ x: 29.932816, y: 11.6 },
]} />
<trace name="U1_MCU_DIO6_A1_to_net_CHG_PG_N" from=".U1_MCU > .DIO6_A1" to="net.CHG_PG_N" />
{/* BMA400 I2C address 0x14, dedicated step and double-tap wake lines. */}
<trace name="U4_ACCEL_VDD_to_net_SYS_VDD" from=".U4_ACCEL > .VDD" to="net.SYS_VDD" /><trace name="U4_ACCEL_VDDIO_to_net_SYS_VDD" from=".U4_ACCEL > .VDDIO" to="net.SYS_VDD" />
<trace name="U4_ACCEL_GND_to_net_GND" from=".U4_ACCEL > .GND" to="net.GND" /><trace name="U4_ACCEL_GNDIO_to_net_GND" from=".U4_ACCEL > .GNDIO" to="net.GND" />
<trace name="U4_ACCEL_CSB_to_net_SYS_VDD" from=".U4_ACCEL > .CSB" to="net.SYS_VDD" /><trace name="U4_ACCEL_SDO_to_net_GND" from=".U4_ACCEL > .SDO" to="net.GND" />
<trace name="U4_ACCEL_SCX_to_net_I2C_SCL" from=".U4_ACCEL > .SCX" to="net.I2C_SCL" /><trace name="U4_ACCEL_SDX_to_net_I2C_SDA" from=".U4_ACCEL > .SDX" to="net.I2C_SDA" />
<trace name="U4_ACCEL_INT1_to_net_ACCEL_INT1" from=".U4_ACCEL > .INT1" to="net.ACCEL_INT1" /><trace name="U4_ACCEL_INT2_to_net_ACCEL_INT2" from=".U4_ACCEL > .INT2" to="net.ACCEL_INT2" />
<trace name="C18_ACCEL_VDD_pin1_to_net_SYS_VDD" from=".C18_ACCEL_VDD > .pin1" to="net.SYS_VDD" /><trace name="C18_ACCEL_VDD_pin2_to_net_GND" from=".C18_ACCEL_VDD > .pin2" to="net.GND" />
<trace name="C19_ACCEL_VDDIO_pin1_to_net_SYS_VDD" from=".C19_ACCEL_VDDIO > .pin1" to="net.SYS_VDD" /><trace name="C19_ACCEL_VDDIO_pin2_to_net_GND" from=".C19_ACCEL_VDDIO > .pin2" to="net.GND" />
<trace name="R12_I2C_SCL_pin1_to_net_I2C_SCL" from=".R12_I2C_SCL > .pin1" to="net.I2C_SCL" /><trace name="R12_I2C_SCL_pin2_to_net_SYS_VDD" from=".R12_I2C_SCL > .pin2" to="net.SYS_VDD" />
<trace name="R13_SDA_to_MCU_fanout" from=".R13_I2C_SDA > .pin1" to=".V_MCU_SDA > .bottom"
pcbPathRelativeTo=".R13_I2C_SDA > .pin1"
pcbPath={[
{ x: -1.5, y: 0 },
{ x: -1.5, y: 0, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: -1.5, y: 0 }, ".V_MCU_SDA > .bottom",
]} />
<trace name="R13_I2C_SDA_pin2_to_net_SYS_VDD" from=".R13_I2C_SDA > .pin2" to="net.SYS_VDD" />
{/* OLED is normally off; the bilateral switch prevents SDA/SCL back-power. */}
<trace name="Q1_DISPLAY_SWITCH_S_to_net_SYS_VDD" from=".Q1_DISPLAY_SWITCH > .S" to="net.SYS_VDD" width="0.3mm" /><trace name="Q1_DISPLAY_SWITCH_D_to_net_DISP_VDD" from=".Q1_DISPLAY_SWITCH > .D" to="net.DISP_VDD" width="0.3mm" />
<trace name="Q1_DISPLAY_SWITCH_G_to_net_DISP_PWR_N" from=".Q1_DISPLAY_SWITCH > .G" to="net.DISP_PWR_N" /><trace name="R14_DISPLAY_GATE_PU_pin1_to_net_DISP_PWR_N" from=".R14_DISPLAY_GATE_PU > .pin1" to="net.DISP_PWR_N" /><trace name="R14_DISPLAY_GATE_PU_pin2_to_net_SYS_VDD" from=".R14_DISPLAY_GATE_PU > .pin2" to="net.SYS_VDD" />
<trace name="U5_DISPLAY_BUS_SWITCH_VCC_to_net_SYS_VDD" from=".U5_DISPLAY_BUS_SWITCH > .VCC" to="net.SYS_VDD" /><trace name="U5_DISPLAY_BUS_SWITCH_GND_to_net_GND" from=".U5_DISPLAY_BUS_SWITCH > .GND" to="net.GND" />
<trace name="U5_DISPLAY_BUS_SWITCH_1A_to_net_I2C_SDA" from=".U5_DISPLAY_BUS_SWITCH > .1A" to="net.I2C_SDA" /><trace name="U5_DISPLAY_BUS_SWITCH_1B_to_net_DISP_SDA" from=".U5_DISPLAY_BUS_SWITCH > .1B" to="net.DISP_SDA" />
<trace name="U5_DISPLAY_BUS_SWITCH_2A_to_net_I2C_SCL" from=".U5_DISPLAY_BUS_SWITCH > .2A" to="net.I2C_SCL" /><trace name="U5_DISPLAY_BUS_SWITCH_2B_to_net_DISP_SCL" from=".U5_DISPLAY_BUS_SWITCH > .2B" to="net.DISP_SCL" />
<trace name="U5_DISPLAY_BUS_SWITCH_1C_to_net_DISP_BUS_EN" from=".U5_DISPLAY_BUS_SWITCH > .1C" to="net.DISP_BUS_EN" /><trace name="U5_DISPLAY_BUS_SWITCH_2C_to_net_DISP_BUS_EN" from=".U5_DISPLAY_BUS_SWITCH > .2C" to="net.DISP_BUS_EN" />
<trace name="R15_DISPLAY_BUS_EN_PD_pin1_to_net_DISP_BUS_EN" from=".R15_DISPLAY_BUS_EN_PD > .pin1" to="net.DISP_BUS_EN" /><trace name="R15_DISPLAY_BUS_EN_PD_pin2_to_net_GND" from=".R15_DISPLAY_BUS_EN_PD > .pin2" to="net.GND" />
<trace name="J3_DISPLAY_DISP_VDD_to_net_DISP_VDD" from=".J3_DISPLAY > .DISP_VDD" to="net.DISP_VDD" width="0.3mm" /><trace name="J3_DISPLAY_GND_to_net_GND" from=".J3_DISPLAY > .GND" to="net.GND" />
<trace name="J3_DISPLAY_SDA_to_net_DISP_SDA" from=".J3_DISPLAY > .SDA" to="net.DISP_SDA" /><trace name="J3_DISPLAY_SCL_to_net_DISP_SCL" from=".J3_DISPLAY > .SCL" to="net.DISP_SCL" /><trace name="J3_DISPLAY_MOUNT_to_net_GND" from=".J3_DISPLAY > .MOUNT" to="net.GND" />
<trace name="C20_DISPLAY_BULK_pin1_to_net_DISP_VDD" from=".C20_DISPLAY_BULK > .pin1" to="net.DISP_VDD" /><trace name="C20_DISPLAY_BULK_pin2_to_net_GND" from=".C20_DISPLAY_BULK > .pin2" to="net.GND" />
{/* TI 1.5 pF / 2.8 nH / 1.5 pF filter, followed by an enclosure-tuning PI. */}
<trace name="U1_ANT_to_L2_RF_FILTER" from=".U1_MCU > .ANT" to=".L2_RF_FILTER > .pin1" width="0.18mm"
pcbPathRelativeTo=".U1_MCU > .ANT"
pcbPath={[{ x: -2.25, y: 1.6 }, { x: -3.516168, y: 1.6 }]} />
<trace name="C21_RF_FILTER_IN_pin1_to_net_RF_FILTER_IN" from=".C21_RF_FILTER_IN > .pin1" to="net.RF_FILTER_IN" width="0.18mm" /><trace name="C21_RF_FILTER_IN_pin2_to_net_GND" from=".C21_RF_FILTER_IN > .pin2" to="net.GND" />
<trace name="L2_RF_FILTER_pin1_to_net_RF_FILTER_IN" from=".L2_RF_FILTER > .pin1" to="net.RF_FILTER_IN" width="0.18mm" /><trace name="L2_RF_FILTER_pin2_to_net_RF_FILTER_OUT" from=".L2_RF_FILTER > .pin2" to="net.RF_FILTER_OUT" width="0.18mm" />
<trace name="C22_RF_FILTER_OUT_pin1_to_net_RF_FILTER_OUT" from=".C22_RF_FILTER_OUT > .pin1" to="net.RF_FILTER_OUT" width="0.18mm" /><trace name="C22_RF_FILTER_OUT_pin2_to_net_GND" from=".C22_RF_FILTER_OUT > .pin2" to="net.GND" />
<trace name="C23_RF_TUNE_IN_pin1_to_net_RF_FILTER_OUT" from=".C23_RF_TUNE_IN > .pin1" to="net.RF_FILTER_OUT" width="0.18mm" /><trace name="C23_RF_TUNE_IN_pin2_to_net_GND" from=".C23_RF_TUNE_IN > .pin2" to="net.GND" />
<trace name="R16_RF_TUNE_SERIES_pin1_to_net_RF_FILTER_OUT" from=".R16_RF_TUNE_SERIES > .pin1" to="net.RF_FILTER_OUT" width="0.18mm" /><trace name="R16_RF_TUNE_SERIES_pin2_to_net_RF_ANT" from=".R16_RF_TUNE_SERIES > .pin2" to="net.RF_ANT" width="0.18mm" />
<trace name="C24_RF_TUNE_OUT_pin1_to_net_RF_ANT" from=".C24_RF_TUNE_OUT > .pin1" to="net.RF_ANT" width="0.18mm" /><trace name="C24_RF_TUNE_OUT_pin2_to_net_GND" from=".C24_RF_TUNE_OUT > .pin2" to="net.GND" />
<trace name="ANT1_ANT_to_net_RF_ANT" from=".ANT1 > .ANT" to="net.RF_ANT" width="0.18mm" />
<McuSignalFanout />
<via name="V_CHARGER_SYS" pcbX={pcbLayout.U2_CHARGER.pcbX - 0.95} pcbY={pcbLayout.U2_CHARGER.pcbY - 1.95}
fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.45mm" connectsTo="net.VSYS_RAW" />
<trace name="U2_SYS_fanout" from=".U2_CHARGER > .SYS" to=".V_CHARGER_SYS > .bottom"
width="0.2mm" pcbPath={[".V_CHARGER_SYS > .bottom"]} />
<via name="V_CHARGER_BAT" pcbX={pcbLayout.U2_CHARGER.pcbX - 0.4} pcbY={pcbLayout.U2_CHARGER.pcbY - 2.65}
fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.45mm" connectsTo="net.BAT_SENSED" />
<trace name="U2_BAT_fanout" from=".U2_CHARGER > .BAT" to=".V_CHARGER_BAT > .bottom"
width="0.2mm" pcbPathRelativeTo=".U2_CHARGER > .BAT"
pcbPath={[{ x: -0.399923, y: -1.55 }, ".V_CHARGER_BAT > .bottom"]} />
<via name="V_CHARGER_CE" pcbX={pcbLayout.U2_CHARGER.pcbX + 0.75} pcbY={pcbLayout.U2_CHARGER.pcbY - 2.25}
fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.45mm" connectsTo="net.CHG_CE_N" />
<trace name="U2_CE_fanout" from=".U2_CHARGER > .N_CE" to=".V_CHARGER_CE > .bottom"
pcbPathRelativeTo=".U2_CHARGER > .N_CE"
pcbPath={[{ x: 0.399923, y: -1.6 }, ".V_CHARGER_CE > .bottom"]} />
<via name="V_CHARGER_PG" pcbX={pcbLayout.U2_CHARGER.pcbX + 0.15} pcbY={pcbLayout.U2_CHARGER.pcbY - 1.95}
fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.45mm" connectsTo="net.CHG_PG_N" />
<trace name="U2_PG_fanout" from=".U2_CHARGER > .PG_GPO" to=".V_CHARGER_PG > .bottom"
pcbPath={[".V_CHARGER_PG > .bottom"]} />
<via name="V_CHARGER_INT" pcbX={pcbLayout.U2_CHARGER.pcbX - 0.4} pcbY={pcbLayout.U2_CHARGER.pcbY + 2}
fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.45mm" connectsTo="net.CHG_INT_N" />
<trace name="U2_INT_fanout" from=".U2_CHARGER > .N_INT" to=".V_CHARGER_INT > .bottom"
pcbPath={[".V_CHARGER_INT > .bottom"]} />
<via name="V_SYS_WEST" pcbX={pcbLayout.U1_MCU.pcbX - 2.8} pcbY={pcbLayout.U1_MCU.pcbY - 1.25}
fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.45mm" connectsTo="net.SYS_VDD" />
<trace name="U1_VDDS2_fanout" from=".U1_MCU > .VDDS2" to=".V_SYS_WEST > .bottom"
width="0.2mm" pcbPath={[".V_SYS_WEST > .bottom"]} />
<via name="V_CHARGER_TS" pcbX={pcbLayout.U2_CHARGER.pcbX + 1.7} pcbY={pcbLayout.U2_CHARGER.pcbY + 1.55}
fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.45mm" connectsTo="net.BATT_NTC" />
<trace name="U2_TS_fanout" from=".U2_CHARGER > .TS_MR" to=".V_CHARGER_TS > .bottom"
pcbPath={[".V_CHARGER_TS > .bottom"]} />
<via name="V_CHARGER_SDA" pcbX={pcbLayout.U2_CHARGER.pcbX + 1.3} pcbY={pcbLayout.U2_CHARGER.pcbY + 2.2}
fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.45mm" connectsTo="net.I2C_SDA" />
<trace name="U2_SDA_fanout" from=".U2_CHARGER > .SDA" to=".V_CHARGER_SDA > .bottom"
pcbPathRelativeTo=".U2_CHARGER > .SDA"
pcbPath={[{ x: 0.399923, y: 1.55 }, ".V_CHARGER_SDA > .bottom"]} />
<copperpour name="GND_TOP" layer="top" connectsTo="net.GND" padMargin="0.2mm" traceMargin="0.15mm"
outline={groundPourOutline} />
<copperpour name="GND_INNER1" layer="inner1" connectsTo="net.GND" padMargin="0.2mm" traceMargin="0.15mm"
outline={groundPourOutline} />
<copperpour name="GND_BOTTOM" layer="bottom" connectsTo="net.GND" padMargin="0.2mm" traceMargin="0.15mm" outline={groundPourOutline} />
<BoardSilkscreen />
</board>
)
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