astra-abse/t113-s3

Allwinner T113-S3 / JLCPCB C5197687: native saved fanout, LCD top, storage right, 127 perimeter exits, 30 decoupling capacitors, connected GND planes; clean DRC and shorts, all 29 vias connected.

Version
1.2.0
License
MIT
Stars
0

scripts/normalize-saved-paths.ts

import { fanoutTracePath } from "@tscircuit/props";
import assert from "node:assert/strict";
const file = "src/generated/lcd_top_storage_right.trace-paths.json";
const paths = ((await Bun.file(file).json()) as unknown[]).map((p) =>
	fanoutTracePath.parse(p),
);
/** Expand via endpoints without moving copper. Board-local mm, +X right, +Y up.
 * Older canvas viewers require explicit wire points on both sides of a via. */
for (const path of paths) {
	const original = path.route;
	const expanded: typeof original = [];
	const add = (p: (typeof original)[number]) => {
		const last = expanded.at(-1);
		if (
			p.route_type === "wire" &&
			last?.route_type === "wire" &&
			p.x === last.x &&
			p.y === last.y &&
			p.layer === last.layer
		)
			expanded[expanded.length - 1] = p;
		else expanded.push(p);
	};
	let width = original.find((p) => p.route_type === "wire")?.width ?? 0.1;
	for (const p of original) {
		if (p.route_type === "wire") {
			width = p.width;
			add(p);
			continue;
		}
		add({ route_type: "wire", x: p.x, y: p.y, layer: p.from_layer, width });
		add(p);
		add({ route_type: "wire", x: p.x, y: p.y, layer: p.to_layer, width });
	}
	assert.deepEqual(
		expanded.filter((p) => p.route_type === "via"),
		original.filter((p) => p.route_type === "via"),
	);
	path.route = expanded;
}
await Bun.write(file, JSON.stringify(paths, null, 2) + "\n");
console.log(
	`Normalized ${paths.length} saved paths; all via coordinates and layer spans unchanged`,
);