astra-abse/t113-s3
Allwinner T113-S3 / JLCPCB C5197687: native saved fanout, LCD top, storage right, 127 perimeter exits, 30 decoupling capacitors, connected GND planes; clean DRC and shorts, all 29 vias connected.
- Version
- 1.2.0
- License
- MIT
- Stars
- 0
tests/handoff.test.tsx
import { test, expect } from "bun:test";
import { Circuit } from "@tscircuit/core";
import { runAllChecks } from "@tscircuit/checks";
import { T113S3Module } from "../src/T113S3Module";
import { elements } from "../scripts/audit";
test("a parent trace connects through the exported storage breakout", async () => {
const circuit = new Circuit();
circuit.add(
<board
width={52}
height={44}
layers={4}
minTraceWidth={0.1}
defaultTraceWidth={0.1}
minTraceToPadEdgeClearance={0.1}
minViaEdgeToPadEdgeClearance={0.1}
minViaHoleDiameter={0.2}
minViaPadDiameter={0.45}
>
<schematicsheet name="Main" sheetWidth={550} sheetHeight={350}>
<T113S3Module
name="SOC"
busProfile="lcd_top_storage_right"
connections={{ SDMMC0_D1: ".J_STORAGE > .pin1" }}
/>
<connector
name="J_STORAGE"
pinCount={1}
pinLabels={{ pin1: "PF0" }}
pinAttributes={{ pin1: { mustBeConnected: true } }}
pcbX={22}
pcbY={-3.800094}
schX={25}
footprint={
<footprint insertionDirection="from_right">
<smtpad portHints={["pin1"]} shape="rect" width={1} height={1} />
<courtyardrect width={2} height={2} />
</footprint>
}
/>
</schematicsheet>
</board>,
);
await circuit.renderUntilSettled();
const json = circuit.getCircuitJson();
expect(json.filter((e) => /error|warning/.test(e.type))).toEqual([]);
expect(await runAllChecks(json)).toEqual([]);
const source = elements(json, "source_trace").find(
(t) => t.name === "SOC_SDMMC0_D1_external",
)!;
const copper = elements(json, "pcb_trace").filter(
(t) => t.source_trace_id === source.source_trace_id,
);
expect(copper.length).toBeGreaterThan(0);
expect(
copper.some((t) =>
t.route.some(
(p) =>
p.route_type === "wire" &&
Math.abs(p.x - 18) < 1e-5 &&
Math.abs(p.y + 3.800094) < 1e-5,
),
),
).toBe(true);
}, 60000);