tscircuit/autorouting-dataset-01
This code manages the hardware and electronic components for circuit design and PCB layout, defining components like resistors, capacitors, transistors, connectors, and footprints, and providing tools for component placement, PCB topology, and electrical connections.
- Version
- 1.0.102
- License
- unset
- Stars
- 4
lib/dataset/circuit011.simple-route.json
{
"bounds": {
"minX": -16,
"maxX": 16,
"minY": -10,
"maxY": 10
},
"obstacles": [
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_0",
"pcb_port_id": "pcb_port_1",
"source_component_name": "J1",
"source_port_name": "VCC"
},
"componentId": "pcb_component_0",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": -10.500127999999904,
"y": 3.9994833000000654
},
"width": 0.5999987999999999,
"height": 1.5500095999999999,
"connectedTo": [
"pcb_smtpad_0",
"connectivity_net36",
"source_trace_16",
"source_port_16",
"source_trace_14",
"source_port_14",
"source_trace_12",
"source_port_12",
"source_trace_8",
"source_port_8",
"source_trace_5",
"source_port_5",
"source_trace_1",
"source_port_1",
"source_net_1",
"pcb_smtpad_0",
"pcb_port_1",
"pcb_smtpad_6",
"pcb_port_5",
"pcb_plated_hole_0",
"pcb_port_8",
"pcb_smtpad_12",
"pcb_port_12",
"pcb_smtpad_14",
"pcb_port_14",
"pcb_smtpad_16",
"pcb_port_16"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_1",
"pcb_port_id": "pcb_port_0",
"source_component_name": "J1",
"source_port_name": "GND"
},
"componentId": "pcb_component_0",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": -9.500130000000013,
"y": 3.9994833000000654
},
"width": 0.5999987999999999,
"height": 1.5500095999999999,
"connectedTo": [
"pcb_smtpad_1",
"connectivity_net38",
"source_trace_17",
"source_port_17",
"source_trace_9",
"source_port_9",
"source_trace_4",
"source_port_4",
"source_trace_0",
"source_port_0",
"source_net_0",
"pcb_smtpad_1",
"pcb_port_0",
"pcb_smtpad_7",
"pcb_port_4",
"pcb_plated_hole_1",
"pcb_port_9",
"pcb_smtpad_17",
"pcb_port_17"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_2",
"pcb_port_id": "pcb_port_3",
"source_component_name": "J1",
"source_port_name": "SCL"
},
"componentId": "pcb_component_0",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": -12.500377999999955,
"y": 3.9999913000000333
},
"width": 0.5999987999999999,
"height": 1.5500095999999999,
"connectedTo": [
"pcb_smtpad_2",
"connectivity_net34",
"source_trace_15",
"source_port_15",
"source_trace_11",
"source_port_11",
"source_trace_7",
"source_port_7",
"source_trace_3",
"source_port_3",
"source_net_3",
"pcb_smtpad_2",
"pcb_port_3",
"pcb_smtpad_8",
"pcb_port_7",
"pcb_plated_hole_3",
"pcb_port_11",
"pcb_smtpad_15",
"pcb_port_15"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_3",
"pcb_port_id": "pcb_port_2",
"source_component_name": "J1",
"source_port_name": "SDA"
},
"componentId": "pcb_component_0",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": -11.500380000000064,
"y": 3.9999913000000333
},
"width": 0.5999987999999999,
"height": 1.5500095999999999,
"connectedTo": [
"pcb_smtpad_3",
"connectivity_net30",
"source_trace_13",
"source_port_13",
"source_trace_10",
"source_port_10",
"source_trace_6",
"source_port_6",
"source_trace_2",
"source_port_2",
"source_net_2",
"pcb_smtpad_3",
"pcb_port_2",
"pcb_smtpad_9",
"pcb_port_6",
"pcb_plated_hole_2",
"pcb_port_10",
"pcb_smtpad_13",
"pcb_port_13"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_4",
"source_component_name": "J1"
},
"componentId": "pcb_component_0",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": -8.199903999999947,
"y": 7.875015299999973
},
"width": 1.1999975999999999,
"height": 1.7999964,
"connectedTo": [
"pcb_smtpad_4"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_5",
"source_component_name": "J1"
},
"componentId": "pcb_component_0",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": -13.800096000000053,
"y": 7.875523300000054
},
"width": 1.1999975999999999,
"height": 1.7999964,
"connectedTo": [
"pcb_smtpad_5"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_6",
"pcb_port_id": "pcb_port_5",
"source_component_name": "J2",
"source_port_name": "VCC"
},
"componentId": "pcb_component_1",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": 11.499872000000096,
"y": 3.9994833000000654
},
"width": 0.5999987999999999,
"height": 1.5500095999999999,
"connectedTo": [
"pcb_smtpad_6",
"connectivity_net36",
"source_trace_16",
"source_port_16",
"source_trace_14",
"source_port_14",
"source_trace_12",
"source_port_12",
"source_trace_8",
"source_port_8",
"source_trace_5",
"source_port_5",
"source_trace_1",
"source_port_1",
"source_net_1",
"pcb_smtpad_0",
"pcb_port_1",
"pcb_smtpad_6",
"pcb_port_5",
"pcb_plated_hole_0",
"pcb_port_8",
"pcb_smtpad_12",
"pcb_port_12",
"pcb_smtpad_14",
"pcb_port_14",
"pcb_smtpad_16",
"pcb_port_16"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_7",
"pcb_port_id": "pcb_port_4",
"source_component_name": "J2",
"source_port_name": "GND"
},
"componentId": "pcb_component_1",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": 12.499869999999987,
"y": 3.9994833000000654
},
"width": 0.5999987999999999,
"height": 1.5500095999999999,
"connectedTo": [
"pcb_smtpad_7",
"connectivity_net38",
"source_trace_17",
"source_port_17",
"source_trace_9",
"source_port_9",
"source_trace_4",
"source_port_4",
"source_trace_0",
"source_port_0",
"source_net_0",
"pcb_smtpad_1",
"pcb_port_0",
"pcb_smtpad_7",
"pcb_port_4",
"pcb_plated_hole_1",
"pcb_port_9",
"pcb_smtpad_17",
"pcb_port_17"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_8",
"pcb_port_id": "pcb_port_7",
"source_component_name": "J2",
"source_port_name": "SCL"
},
"componentId": "pcb_component_1",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": 9.499622000000045,
"y": 3.9999913000000333
},
"width": 0.5999987999999999,
"height": 1.5500095999999999,
"connectedTo": [
"pcb_smtpad_8",
"connectivity_net34",
"source_trace_15",
"source_port_15",
"source_trace_11",
"source_port_11",
"source_trace_7",
"source_port_7",
"source_trace_3",
"source_port_3",
"source_net_3",
"pcb_smtpad_2",
"pcb_port_3",
"pcb_smtpad_8",
"pcb_port_7",
"pcb_plated_hole_3",
"pcb_port_11",
"pcb_smtpad_15",
"pcb_port_15"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_9",
"pcb_port_id": "pcb_port_6",
"source_component_name": "J2",
"source_port_name": "SDA"
},
"componentId": "pcb_component_1",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": 10.499619999999936,
"y": 3.9999913000000333
},
"width": 0.5999987999999999,
"height": 1.5500095999999999,
"connectedTo": [
"pcb_smtpad_9",
"connectivity_net30",
"source_trace_13",
"source_port_13",
"source_trace_10",
"source_port_10",
"source_trace_6",
"source_port_6",
"source_trace_2",
"source_port_2",
"source_net_2",
"pcb_smtpad_3",
"pcb_port_2",
"pcb_smtpad_9",
"pcb_port_6",
"pcb_plated_hole_2",
"pcb_port_10",
"pcb_smtpad_13",
"pcb_port_13"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_10",
"source_component_name": "J2"
},
"componentId": "pcb_component_1",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": 13.800096000000053,
"y": 7.875015299999973
},
"width": 1.1999975999999999,
"height": 1.7999964,
"connectedTo": [
"pcb_smtpad_10"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_11",
"source_component_name": "J2"
},
"componentId": "pcb_component_1",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": 8.199903999999947,
"y": 7.875523300000054
},
"width": 1.1999975999999999,
"height": 1.7999964,
"connectedTo": [
"pcb_smtpad_11"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_12",
"pcb_port_id": "pcb_port_12",
"source_component_name": "R1",
"source_port_name": "pin1"
},
"componentId": "pcb_component_3",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": -5.825,
"y": 0
},
"width": 0.8,
"height": 0.95,
"connectedTo": [
"pcb_smtpad_12",
"connectivity_net36",
"source_trace_16",
"source_port_16",
"source_trace_14",
"source_port_14",
"source_trace_12",
"source_port_12",
"source_trace_8",
"source_port_8",
"source_trace_5",
"source_port_5",
"source_trace_1",
"source_port_1",
"source_net_1",
"pcb_smtpad_0",
"pcb_port_1",
"pcb_smtpad_6",
"pcb_port_5",
"pcb_plated_hole_0",
"pcb_port_8",
"pcb_smtpad_12",
"pcb_port_12",
"pcb_smtpad_14",
"pcb_port_14",
"pcb_smtpad_16",
"pcb_port_16"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_13",
"pcb_port_id": "pcb_port_13",
"source_component_name": "R1",
"source_port_name": "pin2"
},
"componentId": "pcb_component_3",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": -4.175,
"y": 0
},
"width": 0.8,
"height": 0.95,
"connectedTo": [
"pcb_smtpad_13",
"connectivity_net30",
"source_trace_13",
"source_port_13",
"source_trace_10",
"source_port_10",
"source_trace_6",
"source_port_6",
"source_trace_2",
"source_port_2",
"source_net_2",
"pcb_smtpad_3",
"pcb_port_2",
"pcb_smtpad_9",
"pcb_port_6",
"pcb_plated_hole_2",
"pcb_port_10",
"pcb_smtpad_13",
"pcb_port_13"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_14",
"pcb_port_id": "pcb_port_14",
"source_component_name": "R2",
"source_port_name": "pin1"
},
"componentId": "pcb_component_4",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": 4.175,
"y": 0
},
"width": 0.8,
"height": 0.95,
"connectedTo": [
"pcb_smtpad_14",
"connectivity_net36",
"source_trace_16",
"source_port_16",
"source_trace_14",
"source_port_14",
"source_trace_12",
"source_port_12",
"source_trace_8",
"source_port_8",
"source_trace_5",
"source_port_5",
"source_trace_1",
"source_port_1",
"source_net_1",
"pcb_smtpad_0",
"pcb_port_1",
"pcb_smtpad_6",
"pcb_port_5",
"pcb_plated_hole_0",
"pcb_port_8",
"pcb_smtpad_12",
"pcb_port_12",
"pcb_smtpad_14",
"pcb_port_14",
"pcb_smtpad_16",
"pcb_port_16"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_15",
"pcb_port_id": "pcb_port_15",
"source_component_name": "R2",
"source_port_name": "pin2"
},
"componentId": "pcb_component_4",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": 5.825,
"y": 0
},
"width": 0.8,
"height": 0.95,
"connectedTo": [
"pcb_smtpad_15",
"connectivity_net34",
"source_trace_15",
"source_port_15",
"source_trace_11",
"source_port_11",
"source_trace_7",
"source_port_7",
"source_trace_3",
"source_port_3",
"source_net_3",
"pcb_smtpad_2",
"pcb_port_3",
"pcb_smtpad_8",
"pcb_port_7",
"pcb_plated_hole_3",
"pcb_port_11",
"pcb_smtpad_15",
"pcb_port_15"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_16",
"pcb_port_id": "pcb_port_16",
"source_component_name": "C1",
"source_port_name": "pin1"
},
"componentId": "pcb_component_5",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": -0.825,
"y": 0
},
"width": 0.8,
"height": 0.95,
"connectedTo": [
"pcb_smtpad_16",
"connectivity_net36",
"source_trace_16",
"source_port_16",
"source_trace_14",
"source_port_14",
"source_trace_12",
"source_port_12",
"source_trace_8",
"source_port_8",
"source_trace_5",
"source_port_5",
"source_trace_1",
"source_port_1",
"source_net_1",
"pcb_smtpad_0",
"pcb_port_1",
"pcb_smtpad_6",
"pcb_port_5",
"pcb_plated_hole_0",
"pcb_port_8",
"pcb_smtpad_12",
"pcb_port_12",
"pcb_smtpad_14",
"pcb_port_14",
"pcb_smtpad_16",
"pcb_port_16"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_17",
"pcb_port_id": "pcb_port_17",
"source_component_name": "C1",
"source_port_name": "pin2"
},
"componentId": "pcb_component_5",
"type": "rect",
"layers": [
"top"
],
"center": {
"x": 0.825,
"y": 0
},
"width": 0.8,
"height": 0.95,
"connectedTo": [
"pcb_smtpad_17",
"connectivity_net38",
"source_trace_17",
"source_port_17",
"source_trace_9",
"source_port_9",
"source_trace_4",
"source_port_4",
"source_trace_0",
"source_port_0",
"source_net_0",
"pcb_smtpad_1",
"pcb_port_0",
"pcb_smtpad_7",
"pcb_port_4",
"pcb_plated_hole_1",
"pcb_port_9",
"pcb_smtpad_17",
"pcb_port_17"
]
},
{
"circuitJsonMetadata": {
"pcb_plated_hole_id": "pcb_plated_hole_0",
"pcb_port_id": "pcb_port_8",
"source_component_name": "J3",
"source_port_name": "pin1"
},
"componentId": "pcb_component_2",
"type": "rect",
"layers": [
"top",
"bottom"
],
"center": {
"x": -2.3329521523757077e-16,
"y": -9.01
},
"width": 1.5,
"height": 1.5,
"connectedTo": [
"pcb_plated_hole_0",
"connectivity_net36",
"source_trace_16",
"source_port_16",
"source_trace_14",
"source_port_14",
"source_trace_12",
"source_port_12",
"source_trace_8",
"source_port_8",
"source_trace_5",
"source_port_5",
"source_trace_1",
"source_port_1",
"source_net_1",
"pcb_smtpad_0",
"pcb_port_1",
"pcb_smtpad_6",
"pcb_port_5",
"pcb_plated_hole_0",
"pcb_port_8",
"pcb_smtpad_12",
"pcb_port_12",
"pcb_smtpad_14",
"pcb_port_14",
"pcb_smtpad_16",
"pcb_port_16"
]
},
{
"circuitJsonMetadata": {
"pcb_plated_hole_id": "pcb_plated_hole_1",
"pcb_port_id": "pcb_port_9",
"source_component_name": "J3",
"source_port_name": "pin2"
},
"componentId": "pcb_component_2",
"type": "oval",
"layers": [
"top",
"bottom"
],
"center": {
"x": -7.776507174585693e-17,
"y": -6.470000000000001
},
"width": 1.5,
"height": 1.5,
"connectedTo": [
"pcb_plated_hole_1",
"connectivity_net38",
"source_trace_17",
"source_port_17",
"source_trace_9",
"source_port_9",
"source_trace_4",
"source_port_4",
"source_trace_0",
"source_port_0",
"source_net_0",
"pcb_smtpad_1",
"pcb_port_0",
"pcb_smtpad_7",
"pcb_port_4",
"pcb_plated_hole_1",
"pcb_port_9",
"pcb_smtpad_17",
"pcb_port_17"
]
},
{
"circuitJsonMetadata": {
"pcb_plated_hole_id": "pcb_plated_hole_2",
"pcb_port_id": "pcb_port_10",
"source_component_name": "J3",
"source_port_name": "pin3"
},
"componentId": "pcb_component_2",
"type": "oval",
"layers": [
"top",
"bottom"
],
"center": {
"x": 7.776507174585693e-17,
"y": -3.93
},
"width": 1.5,
"height": 1.5,
"connectedTo": [
"pcb_plated_hole_2",
"connectivity_net30",
"source_trace_13",
"source_port_13",
"source_trace_10",
"source_port_10",
"source_trace_6",
"source_port_6",
"source_trace_2",
"source_port_2",
"source_net_2",
"pcb_smtpad_3",
"pcb_port_2",
"pcb_smtpad_9",
"pcb_port_6",
"pcb_plated_hole_2",
"pcb_port_10",
"pcb_smtpad_13",
"pcb_port_13"
]
},
{
"circuitJsonMetadata": {
"pcb_plated_hole_id": "pcb_plated_hole_3",
"pcb_port_id": "pcb_port_11",
"source_component_name": "J3",
"source_port_name": "pin4"
},
"componentId": "pcb_component_2",
"type": "oval",
"layers": [
"top",
"bottom"
],
"center": {
"x": 2.3329521523757077e-16,
"y": -1.3900000000000001
},
"width": 1.5,
"height": 1.5,
"connectedTo": [
"pcb_plated_hole_3",
"connectivity_net34",
"source_trace_15",
"source_port_15",
"source_trace_11",
"source_port_11",
"source_trace_7",
"source_port_7",
"source_trace_3",
"source_port_3",
"source_net_3",
"pcb_smtpad_2",
"pcb_port_3",
"pcb_smtpad_8",
"pcb_port_7",
"pcb_plated_hole_3",
"pcb_port_11",
"pcb_smtpad_15",
"pcb_port_15"
]
}
],
"connections": [
{
"name": "source_net_0",
"nominalTraceWidth": 0.1,
"width": 0.1,
"pointsToConnect": [
{
"x": -9.500130000000013,
"y": 3.9994833000000654,
"layer": "top",
"pointId": "pcb_port_0",
"pcb_port_id": "pcb_port_0",
"port_selector": "J1.GND"
},
{
"x": 12.499869999999987,
"y": 3.9994833000000654,
"layer": "top",
"pointId": "pcb_port_4",
"pcb_port_id": "pcb_port_4",
"port_selector": "J2.GND"
},
{
"x": -7.776507174585693e-17,
"y": -6.470000000000001,
"layer": "top",
"pointId": "pcb_port_9",
"pcb_port_id": "pcb_port_9",
"port_selector": "J3.pin2"
},
{
"x": 0.825,
"y": 0,
"layer": "top",
"pointId": "pcb_port_17",
"pcb_port_id": "pcb_port_17",
"port_selector": "C1.pin2"
}
]
},
{
"name": "source_net_1",
"nominalTraceWidth": 0.1,
"width": 0.1,
"pointsToConnect": [
{
"x": -10.500127999999904,
"y": 3.9994833000000654,
"layer": "top",
"pointId": "pcb_port_1",
"pcb_port_id": "pcb_port_1",
"port_selector": "J1.VCC"
},
{
"x": 11.499872000000096,
"y": 3.9994833000000654,
"layer": "top",
"pointId": "pcb_port_5",
"pcb_port_id": "pcb_port_5",
"port_selector": "J2.VCC"
},
{
"x": -2.3329521523757077e-16,
"y": -9.01,
"layer": "top",
"pointId": "pcb_port_8",
"pcb_port_id": "pcb_port_8",
"port_selector": "J3.pin1"
},
{
"x": -5.825,
"y": 0,
"layer": "top",
"pointId": "pcb_port_12",
"pcb_port_id": "pcb_port_12",
"port_selector": "R1.pin1"
},
{
"x": 4.175,
"y": 0,
"layer": "top",
"pointId": "pcb_port_14",
"pcb_port_id": "pcb_port_14",
"port_selector": "R2.pin1"
},
{
"x": -0.825,
"y": 0,
"layer": "top",
"pointId": "pcb_port_16",
"pcb_port_id": "pcb_port_16",
"port_selector": "C1.pin1"
}
]
},
{
"name": "source_net_2",
"nominalTraceWidth": 0.1,
"width": 0.1,
"pointsToConnect": [
{
"x": -11.500380000000064,
"y": 3.9999913000000333,
"layer": "top",
"pointId": "pcb_port_2",
"pcb_port_id": "pcb_port_2",
"port_selector": "J1.SDA"
},
{
"x": 10.499619999999936,
"y": 3.9999913000000333,
"layer": "top",
"pointId": "pcb_port_6",
"pcb_port_id": "pcb_port_6",
"port_selector": "J2.SDA"
},
{
"x": 7.776507174585693e-17,
"y": -3.93,
"layer": "top",
"pointId": "pcb_port_10",
"pcb_port_id": "pcb_port_10",
"port_selector": "J3.pin3"
},
{
"x": -4.175,
"y": 0,
"layer": "top",
"pointId": "pcb_port_13",
"pcb_port_id": "pcb_port_13",
"port_selector": "R1.pin2"
}
]
},
{
"name": "source_net_3",
"nominalTraceWidth": 0.1,
"width": 0.1,
"pointsToConnect": [
{
"x": -12.500377999999955,
"y": 3.9999913000000333,
"layer": "top",
"pointId": "pcb_port_3",
"pcb_port_id": "pcb_port_3",
"port_selector": "J1.SCL"
},
{
"x": 9.499622000000045,
"y": 3.9999913000000333,
"layer": "top",
"pointId": "pcb_port_7",
"pcb_port_id": "pcb_port_7",
"port_selector": "J2.SCL"
},
{
"x": 2.3329521523757077e-16,
"y": -1.3900000000000001,
"layer": "top",
"pointId": "pcb_port_11",
"pcb_port_id": "pcb_port_11",
"port_selector": "J3.pin4"
},
{
"x": 5.825,
"y": 0,
"layer": "top",
"pointId": "pcb_port_15",
"pcb_port_id": "pcb_port_15",
"port_selector": "R2.pin2"
}
]
}
],
"layerCount": 2,
"minTraceWidth": 0.1,
"minViaDiameter": 0.3,
"minViaHoleDiameter": 0.2,
"minViaPadDiameter": 0.3,
"min_via_hole_diameter": 0.2,
"min_via_pad_diameter": 0.3,
"minTraceToPadEdgeClearance": 0.1,
"minViaHoleEdgeToViaHoleEdgeClearance": 0.1,
"minPlatedHoleDrillEdgeToDrillEdgeClearance": 0.15,
"minPadEdgeToPadEdgeClearance": 0.1,
"minBoardEdgeClearance": 0.2
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